The present invention relates to the field of automatic test equipment and simulation instrumentation for testing electronic devices, and more particularly, to automatic test equipment for generating programmable low noise, low spurious, spectrally pure signals in the frequency range of LF (low frequency 30-300 kHz) to HF (high frequency 3-30 MHz).
Automatic test equipment for testing Analog to Digital Converting (ADC) devices is known. However, when the requirements of the ADC devices are such that low spurious, high dynamic range and high-speed conversion is required, then the current state of the art instrumentation in the automatic test equipment is inadequate to perform the required testing operations.
Fixed tuned oscillators meeting these requirements may be substituted for the automatic test equipment and may provide some test capability. However, only true programmable instrumentation can perform wide-band device evaluation.
Direct digital frequency synthesis (DDFS) is a known technique for generating a precisely-controlled, fast frequency switching, frequency accurate, radio frequency (R-F) output. There presently exist various narrow band DDFS integrated circuits that provide frequency and phase control with fractional Hertz and radian resolution, with reasonable spurious performance (xe2x88x9260 decibels below carrier (dBC)). Narrow band DDFS has applications in signal simulation. However, the application is limited due to the inherent narrow RF output bandwidth. Wide-band DDFS integrated circuits exist that provide frequency control only, but these circuits have comparatively poor spurious performance (xe2x88x9230 dBC).
With respect to prior art related to direct digital synthesizers, U.S. Pat. No. 5,789,950 (Nakagawa) describes a direct digital synthesizer capable of generating a desired frequency with small circuitry, low power consumption, and no spurious components. It includes an accumulator for accumulating a frequency control word for each pulse of a clock signal, a D/A converter for converting the accumulation value of the accumulator to an analog voltage, an integrator for smoothing the output of the D/A converter, a comparator for comparing the output of the integrator with a reference voltage, and for producing pulses at timings at which the output of the integrator reaches the reference voltage while the accumulation value of the accumulator is increasing, and a pulse generator for producing pulses in synchronism with the rising edges of the output of the comparator. The output pulses of the pulse generator constitute an output of the direct digital synthesizer.
With respect to prior signal generating devices and methods, early waveform generating devices usually employed a crystal oscillator as the waveform generating device for the system clock and this included a programmable frequency divider, counter, multiplexer, controller and digital-to-analog converter, as well as various devices and methods for generating a waveform by phase accumulation. Improvements in waveform generating devices include U.S. Pat. No. 5,446,760 (Bienz et al.) which describes a digital pulse shaping and phase modulation network for reducing out-of-band spectral energy. The network is used in conjunction with a numerically controlled oscillator. The modulator includes RAM memory having prestored values corresponding to a number of steps relating to changes in digital data inputs and is operated in response to counter outputs to transmit the prestored values. A phase accumulator is coupled to the RAM memory and continuously adds each transmitted prestored value to produce a digital accumulated phase angle.
U.S. Pat. No. 5,428,308 (Maeda) describes a direct digital synthesizer which generates signals having a relatively high frequency and includes a clock generator, a frequency setting circuit in which phase increment for unit clock can be programmed, a phase accumulator in which phase increment is accumulated, a ROM which outputs a digital signal corresponding to cumulative phase output and digital-to-analog converter which inverts polarity of output in each clock time and a band-pass filter.
U.S. Pat. No. 5,883,530 (Wu) describes methods and devices for generating cycled waveforms in which one or more digital waveform sampling values is/are filled into a table. Each sampling value is added/subtracted with a predetermined DC voltage level by an adder/subtracter to obtain a periodic digital value that is then converted into a desired analog waveform by a digital-to-analog converter.
Additional patents which describe other types of signal generators are U.S. Pat. No. 5,349,310 (Rieder et al.), U.S. Pat. No. 5,467,294 (Hu et al.), U.S. Pat. No. 5,519,343 (Britz), U.S. Pat. No. 5,631,586 (Sogo), U.S. Pat. No. 5,703,540 (Gazda et al.), U.S. Pat. No. 5,705,945 (Wee), U.S. Pat. No. 5,821,816 (Patterson), U.S. Pat. No. 5,898,325 (Crook et al.) and U.S. Pat. No. 6,066,967 (Cahill et al.). All of the foregoing patents are incorporated by reference herein in their entirety.
Accordingly, it is an object of the present invention to provide new and improved automatic test instrument for generating spectrally pure programmable signals.
It is another object of the present invention to provide new and improved automatic test equipment for testing ADCS.
It is yet another object of the invention to provide new and improved automatic test equipment capable of testing ADCs having low spurious, high dynamic range and high-speed conversion requirements.
It is another object of the present invention to provide new and improved devices and methods for generating signals, e.g., for testing ADCs, without using a phase accumulator.
In order to achieve the objects set forth above, and others, the automatic test equipment in accordance with the invention comprises a digital data processing (DDP) module that is preferably enclosed in a rack mountable IEEE488 programmable instrument. This module comprises the following major elements: a microprocessor controller, an interface controller, an 80 MHz Bias/DDS (direct digital synthesizer) CCA (circuit card assembly), an 80 MHz oven controlled crystal oscillator (OCXO), a target generator controller, a clock distribution, a target gain programmable filter/trigger, unique waveform software, and an amplifier interface.
In order to obtain the preferred low noise, low spurious, spectrally pure signals, a signal source as perfect as possible should be used. The fixed tuned OCXO has been found to be an exception signal source to obtain low spurious, spectrally pure signal. Other signal sources could be used in certain embodiments of the invention, although the quality of the output signals would likely be lower relative to the quality obtained using an OCXO. The device for generating a spectrally pure waveform of a desired frequency comprises an oven controlled crystal oscillator for generating a reference frequency signal, a waveforn memory containing data on the waveform, a segment determination circuit for creating segments of the waveform in the waveform memory based on the reference frequency signal and the desired frequency, a RAM memory for receiving and storing the segments of the waveform in dedicated address memories, a digital-to-analog converter for downloading the address memories of the RAM memory and forming analog signals, and a filtering component for filtering the analog signals to obtain the waveform of the desired frequency. Instead of the RAM memory, any type of programmable memory may be used. A clock generator/distributor is usually interposed between the oscillator and the waveform memory and segment determination circuit. An amplifier, preferably a linear amplification circuit, is arranged in association with the digital-to-analog converter for amplifing the analog signals. The filtering component might include one or more band-pass filters or one or more pre-selectors. The waveform memory includes data on sine waves, square waves and triangle waves, as well as other types of waveforms. The digital-to-analog converter is preferbaly a 16 bit BiCMOS.
The method for generating a waveform at a particular frequency in accordance with the invention which occurs in the target generator controller comprises the steps of providing a register (designated n) having a value of 0 and clock value of 20 MHz/2n, determining whether the frequency times 4096 is less than or equal to the clock value, incrementing the register until the frequency times 4096 is less than or equal to the clock value, then assigning a segment RAM depth to be equal to the nearest, lower integer of the clock value or frequency, providing a RAM based memory system with waveform information, and generating the waveform from sequential memory from a combination of the waveform information in the RAM based memory system from a first memory site to a memory site dependent on the segment RAM depth. The generated waveform is filtered to obtain only the waveform at the desired frequency. The RAM based memory system is provided with the waveform information by dividing each desired waveform into segments depending on the clock value and storing each of the segments in a respective memory site.
In the method for evaluating an analog to digital converter, the generated waveform which includes the desired frequency and a frequency of a clock rate adjusted by the desired frequency is directed to a filter to remove the frequency of the clock rate adjusted by the desired frequency to thereby obtain only the desired frequency which is directed to the analog to digital converter. The generated waveform is tuned in the filter to a center frequency if it is a sinewave or a tuned squarewave.